The present invention relates to a semiconductor device and a method of manufacturing it, for example, those applicable to manufacture of a semiconductor device having a nonvolatile memory.
As an electrically writable/erasable nonvolatile semiconductor memory device, an EEPROM (electrically erasable and programmable read only memory) has been used widely. Such a memory device has, below the gate electrode of a MISFET, a conductive floating gate electrode or a trapping insulating film surrounded by an oxide film. A charge storage state in the floating gate electrode or trapping insulating film (charge retention portion) is used as stored data and read out as the threshold value of the transistor.
The trapping insulating is an insulating film capable of storing charges therein, and a silicon nitride film is one example of it. By injection/release of charges into/from such a charge storage region, the threshold value of the MISFET is shifted to allow the MISFET to operate as a memory element. Examples of a nonvolatile semiconductor memory device using this trapping insulating film include a split-gate cell using a MONOS (metal oxide nitride oxide semiconductor) film.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2006-332143) describes a split gate type MONOS memory whose memory gate electrode is formed on a surface which is a main surface of a semiconductor substrate and at the same time, is a second surface lower than a first surface of the semiconductor substrate right below a control gate electrode.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2008-288503) describes a split-gate type MONOS memory which performs an erase operation using FN tunneling.
Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2009-010104) describes forming both a data memory cell and a code memory cell on a semiconductor substrate.